The present invention relates to a semiconductor memory which is characterized in its memory cell selecting mechanism, and more particularly to a semiconductor memory using MOS transistors.
In a random access memory such as a semiconductor memory, the number of address signal lines required for each multiplication of the memory capacity is increased one by one. Therefore, the restriction to the number of the pins of a package raises a problem when it is intended to increase the capacity of the semiconductor memory per chip.
In order to solve that problem, the so-called "multiplexed address inputs" mechanism is known to the prior art and is generally used in a MOS memory of large capacity. This is a mechanism which is made operative to receive the signals respectively indicating the column and row addresses in the address plane of the memory in a time-division manner from a set of pins. For example, in the MOS memory which is disclosed in "Digest of 1977 IEEE International Solid State Circuit Conference", on pages 12 and 13, both a first address signal indicating the row address and a second address signal indicating the column address are fed in a time dividing manner to a single set of seven address buffers which are provided commonly therefor. Those address buffers are connected with the row decoder by a set of internal address lines and with the column decoder by another set of internal address lines through a set of switches. When the first address signal and then a row address strobe are fed to the address buffers, the decoding operation is performed by the row decoder. During this operation, the aforementioned switches are non-conducting. Next, when the second address signal and then a column address strobe are fed to the address buffers from the outside, the aforementioned switches are turned on to effect the decoding operation by the column decoder. Thus, the row and column decoders consecutively respond until one of the memory cells is selected. On the other hand, in the MOS memory which is disclosed in Japanese Laid-Open of Patent Application No. 55-15793 (in 1980) and U.S. Pat. No. 4,316,263, means for disabling the column decoder upon reception of the first address signal is provided to lower the load capacity of the address buffers thereby to speed up the memory access.